H57V2562GTR
技术资料——
H57V2562GTR PDF技术资料
| H57V2562GTR 性能参数 | |
|---|---|
| 容量 | 256Mb |
| 结构 | 4Banks x 4Mbits x16 |
| 接口 | LVTTL |
| 工作电压 (V) | 3.3 |
| 工作温度范围 | 0 to 70 °C (商业级) |
| CAS Latency | 3 |
| H57V2562GTR 封装与引脚 | |
| TSOPII54 | |
H57V2562GTR 概述
H57V2562GTR Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for the consumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 4,194,304 x 16 I/O.
H57V2562GTR 特性
- Standard SDRAM Protocol
- Internal 4bank operation
- Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V
- All device pins are compatible with LVTTL interface
- Low Voltage interface to reduce I/O power
- 8,192 Refresh cycles / 64ms
- Programmable CAS latency of 2 or 3
- Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
- Commercial Temp : 0 to 70 °C
- Package Type : 54_Pin TSOPII
- This product is in compliance with the directive pertaining of RoHS
